Integrated circuit devices typically have a number of input/output pins to generate output signals. Output signals of an integrated circuit are typically switched simultaneously in response to a clock signal. Such simultaneously switching of outputs lead to large transient currents, which are often difficult to control. In particular, power and ground noise is generated in on-chip power and ground buses when the signals at the outputs switch logic states simultaneously. When a significant number of drivers switch at the same time, an increased current draw on the power supply may cause a dip or negative spike in the voltage supply to the chip. This dip in power supply voltage may propagate as noise through both active and quiet drivers, and may cause false switching in the system. With system speeds increasing and the demands to transmit more data, destructive simultaneous switching noise has become a greater concern.
Conventional methods control the large transient currents associated with simultaneously switched outputs by controlling the slew rate of the output signals. For example, a staged driver may be implemented, where a portion of the driver is turned on after a fixed delay to reduce the simultaneous switching noise. A chain of inverters has been used in conventional devices to provide a delay to control the slew rate. The transistors of the inverters in the delay circuit have a turn-on time which is dependent upon the bias voltage of the transistor. As the bias voltage varies, the delay provided by the delay stage comprising inverters will vary. For example, a transistor will turn on faster with a higher bias voltage, while the transistor will turn on slower with a lower bias voltage. Accordingly, the use of inverters in delay stages of input/output ports leads to variable delays depending upon the supply voltage.
Simultaneously switched outputs affect many different types of integrated circuits. For example, a programmable logic device is one type of integrated circuit which is designed to be user-programmable so that users may implement logic designs of their choices. One type of programmable logic device is a Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to that used in a Programmable Logic Array (PLA) or a Programmable Array Logic (PAL) device. Another type of programmable logic device is a field programmable gate array (FPGA). In a typical FPGA, an array of configurable logic blocks (CLBs) is coupled to programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a hierarchy of programmable routing resources. For both of these types of programmable logic devices, the functionality of the device is controlled by configuration data bits of a configuration bitstream provided to the device for that purpose.
While programmable logic devices are beneficial because they enable the implementation of a variety of circuits selected by a user, such flexibility creates challenges in implementing input/output ports. That is, because a programmable logic device is intended to incorporate a variety of circuits, a wide range of I/O interfaces needs to be supported on a single I/O structure. However, because a delay created by a delay stage of a conventional circuit varies based upon voltage, providing a known delay for reducing simultaneous switching noise using a conventional circuit is difficult. Further, as operating voltages for some applications continue to decrease, the delay necessary in the I/O ports needs to be reduced. That is, because the switching speed of transistors is reduced at lower operating voltages, a delay may not be necessary. For example, in higher performance I/O interfaces employed in memory applications using lower operating voltages, such as voltages of 1.5 or 1.8 volts, it may not be necessary to use a delay to eliminate simultaneous switching noise. Therefore, the performance of I/O interfaces needs to be improved by maintaining a fixed delay which is independent of a bias voltage, and minimizing the delay for certain lower bias voltages.
Accordingly, there is a need for an improved circuit for and method of generating a delay in an input/output port of an integrated circuit device.